I work on a high-level simulator written in C++ for some hardware that is written in System Verilog.
The System Verilog code includes a number of functions that contain only logic (that is, nothing time-consuming, no flip-flops). I want to reuse this code in my C++ simulator.
Is there any way to reuse these functions in C++ (or C, which is easily linked into C++) by way of:
- Converting System Verilog to C/C++ before compilation?
- Compiling the System Verilog to functions callable by C/C++?
- Any other way?