How can I check with if (…) then … end if; construction if std_logic_vector variable holds the bits of a negative number? If it is negative, I have to assign it a zero value.

I have :

```
signal sum : std_logic_vector (15 downto 0);
sum<= (...);
if (...) then
sum<=x"00";
end if;
```

Thank you!

## Best Solution

You cannot add two

`STD_LOGIC_VECTOR`

s, because the language does not know anything about the arithmetic that it should perform. This is because, to the synthesis tool, every signal/port/variable that's declared as`STD_LOGIC_VECTOR`

is nothing more than an array of`STD_LOGIC`

, the multi-valued logic type. Arithmetic on such a type does not make sense.If you want to use arithmetic on types whose interface is similar to the one exposed by

`STD_LOGIC_VECTOR`

, you should use`SIGNED`

(for signed arithmetic) and`UNSIGNED`

(for unsigned arithmetic) types defined in`IEEE.NUMERIC_STD`

. In order to convert between these types, just cast them using the type names explicitly, like this :So, summing it all up - the

`signal sum`

should be declared as`SIGNED`

, since you're obviously going to perform arithmetic on it. Then, you can freely use the comparison and arithmetic operations that you need. The resulting code should look more or less like this :