Instantiate Modules in Generate For Loop in Verilog

system-verilogverilog

I'm trying to instantiate some modules in Verilog using a generate block since I'm going to be instantiating a variable amount of them.

genvar i;
generate
    for (i=1; i<=10; i=i+1) begin
    status whatever_status (
        .clk(clk),
        .reset_n(reset_n),
        .a(a[i]),
        .b(b[i]),
        .out(out[i])
    );
end 
endgenerate

a & b are declared as input arrays to the parent module and out is declared as a array of wires.

What am I doing wrong here? Is this not allowed in Verilog? Quartus is telling me:

Error (10644): Verilog HDL error at driver.v(63): this block requires a name

Line 63 is the for loop above. Any help is appreciated!

Best Solution

You can apply label identifier to begin-end block with a colon after the begin (example: begin : label - end. This has always been an optional feature for generate blocks, though it is highly recommended. Quartus should not be giving an error.

It is an easy fix to satisfy Quartus-- add a label of any name you want:

genvar i;
generate
    for (i=1; i<=10; i=i+1) begin : generate_block_identifier // <-- example block name
    status whatever_status (
        .clk(clk),
        .reset_n(reset_n),
        .a(a[i]),
        .b(b[i]),
        .out(out[i])
    );
end 
endgenerate
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