The point of a “plain” begin-end block

system-verilogverilog

I'm reading some third party Verilog, and found this:

function [31:0] factorial;
    input [3:0] operand;
    reg [3:0] index;

    begin
        factorial = operand ? 1 : 0;
        for(index = 2; index <= operand; index = index + 1)
        factorial = index * factorial;
    end
endfunction

It seems that the begin and end keywords are redundant here. Are they? What is their use?

Best Solution

I don't know about the general case, but in this specific case:

If a function contains more than one statement, the statements must be
enclosed in a begin-end or fork-join block. 

Source: Verilog Golden Reference Guide

Related Question