In principle, the representation of a VHDL integer is undefined.
In practice, you can normally assume that a synthesis tool will use a 2's complement representation, taking into account the range constraint. Therefore, the relation between the range constraint and the implemented bit width is straightforward, even though reporting the bit width from within VHDL is not.
The error message tells you exactly what the problem is:
error : Error (10381): VHDL Type Mismatch error at ArrayDivider.vhd(53): indexed name returns a value whose type does not match "std_ulogic", the type of the target expression
And indeed, tempz(Ny-2 downto 0)
is not a std_ulogic but a vector.
The problem is that named association does not identify slices of a vector but individual elements; you can't use it to assign one slice of one vector to a slice of another vector.
Instead, use the concatenation operator &
,
tempx <= tempz(Ny-2 downto 0) & ipx(a-1);
Your post implies that concatenation produces other errors; feel free to add these to the question.
EDIT :
>Error (10028): Can't resolve multiple constant drivers for net
>"tempx[0]" at ArrayDivider.vhd(44) (on the line of initialing >tempx)
Again this tells you what is wrong. This error is almost certainly there in both versions of the design, but the original error just hides it. Find the two drivers for tempx(0) and eliminate whichever is the wrong one. You haven't posted enough of your code to make it clear what's going on so that is up to you. If you're using Modelsim, the "drivers" command will identify all the drivers on a signal.
If you need to initialise tempx to the input signal and then later drive it with another signal, you must select between the two signals - for example:
tempx <= ipx(Nx-1 downto Nx-Ny) when <some condition>
else tempz(Ny-2 downto 0) & ipx(a-1);
Most likely, fixing this error will also eliminate the "hierarchy" error; which is basically "something went wrong earlier so compilation cannot be completed".
Best Answer
First of all, the error is because the number as you have written it is treated as an integer.
I take that you mean for the number to be binary? In that case use "".
You can also go for hex, x"".
If you want to assign an integer to an std_logic_vector, then you can do it like this.
Where 12345 is the integer (or natural) and 16 is the width.